The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a pattern in a semiconductor device.
In a conventional method for forming a pattern in a semiconductor device, a bit line hard mask is patterned and then a bottom metal electrode and a polysilicon layer are etched using the bit line hard mask as an etch mask to form bit line patterns. However, upper portions of the bit line patterns are often damaged while etching the bottom layers using the bit line hard mask as an etch mask. Thus, a mask pattern formed for patterning the bit line hard mask is not removed and is used as an etch mask for etching the bottom layers such that the upper portions of the bit line patterns are not damaged.
FIGS. 1A and 1B illustrate cross-sectional views of a conventional method for forming a pattern in a semiconductor device.
Referring to FIG. 1A, an insulation layer 12 is formed over a substrate 11. A barrier metal layer 13 and a metal electrode layer 14 are sequentially formed over the insulation layer 12. A hard mask layer is formed over the metal electrode layer 14. The hard mask layer is patterned to form bit line hard masks 15. The bit line hard masks 15 may be formed after forming a mask pattern 16 over the hard mask layer. The mask pattern 16 may include a stack structure including an amorphous carbon layer, an anti-reflective coating layer, and a photoresist pattern. The anti-reflective coating layer may include silicon oxynitride (SiON).
Referring to FIG. 1B, the metal electrode layer 14 and the barrier metal layer 13 are etched to form bit line patterns using the mask pattern 16 as an etch barrier. Thus, the bit line patterns each include a barrier metal 13A, a metal electrode 14A, and the bit line hard mask 15.
In the aforementioned conventional method, the mask pattern 16 is not removed after forming the bit line hard masks 15. The mask pattern 16 is used to pattern the metal electrode layer 14 and the barrier metal layer 13 in order to reduce damage to upper portions of the bit line patterns.
However, polymers 17 (FIG. 1A) may form on sidewalls of the mask pattern 16 and the bit line hard masks 15 while forming the bit line hard masks 15, thereby generating a sloped profile. When the etching of the bottom layers is performed, the polymers 17 function as an etch mask, resulting in a width W12 of the bit line patterns which is larger than a width W11 of the bit line hard masks 15.
As the width W12 of the bit line patterns increases, a failure of a self-aligned contact (SAC) may occur when forming subsequent storage node contact holes due to a decreased margin of space between the bit line patterns.